1. Field of the Invention
The present invention relates to electrostatic discharge protection for an integrated circuit, and more specifically, to a method and structure for providing ESD protection for an integrated circuit fabricated in accordance with silicon on insulator technology.
2. Description of the Related Art
FIG. 1 is a schematic diagram of a conventional integrated circuit electrostatic discharge (ESD) device 100 which is coupled between input pad 101 and integrated circuit logic circuitry 102. ESD device 100 includes a resistor 103 and an n-channel field effect transistor 104 coupled in series between input pad 101 and Vss voltage supply terminal 105. Vdd voltage supply terminal 106 is coupled to the substrate on which transistor 104 is fabricated, thereby forming diode 107 between Vdd voltage supply terminal 106 and Vss voltage supply terminal 105. ESD device 100 protects integrated circuit logic circuitry 102 by providing current paths through transistor 104 and diode 107 when high positive or negative voltages (relative to the normal operating voltages of Vss and Vdd voltage supply terminals 105, 106) exist on input pad 101, Vss voltage supply terminal 105 or Vdd voltage supply terminal 106.
FIG. 2 is a cross sectional view of transistor 104, including p-substrate 200, n type drain region 201, n type source region 202, gate oxide 203, gate electrode 204, p type substrate contact region 205 and n type diffusion contact region 207. Because transistor 104 is fabricated in bulk silicon (i.e., substrate 200), a parasitic P/N junction exists between substrate 200 and drain region 201. Consequently, if a high voltage is applied to Vss voltage supply terminal 105 (with respect to the voltage applied to input pad 101), an electrically conductive path is formed between Vss voltage supply terminal 105 and input pad 101 through this parasitic P/N junction and resistor 103. This electrically conductive path allows a high current to flow between Vss voltage supply terminal 105 and input pad 101 without damaging logic circuitry 102. Transistor 104 also turns on during these conditions, providing an alternate path between Vss voltage supply terminal 105 and input pad 101.
Additionally, if a high voltage is applied to Vdd voltage supply rail 106 (with respect to the voltage applied to input pad 101), current will flow from n type region 207 to n type region 201 through p-substrate 200 (with the P/N junction formed by region 207 and substrate 200 being operated in reverse breakdown mode). Similarly, if a high voltage is applied to input pad 101 (with respect to the voltage applied to Vdd voltage supply rail 106), current will flow from n type region 201 to n type region 207 through p--substrate 200 (with the P/N junction formed by region 201 and substrate 200 being operated in reverse breakdown mode).
Thus, parasitic P/N junctions formed in devices fabricated in bulk silicon (hereinafter referred to as bulk devices) are useful in providing ESD protection at the input terminals of integrated circuits. However, in utilizing parasitic P/N junctions to provide ESD protection, unpredictable results are sometimes obtained because the circuit designer may not understand the relationships between all of the parasitic P/N junctions present within a circuit.
FIG. 3 is a cross sectional view of an n-channel transistor 300 fabricated in accordance with conventional silicon on insulator (SOI) technology (hereinafter referred to as an SOI transistor or an SOI device). SOI transistor 300 includes insulating substrate 306 on which is formed a thin layer of silicon 310. N type drain region 301, p-type channel region 302 and n type source region 303 are formed in silicon layer 310. Gate oxide 304 and gate electrode 305 are fabricated over silicon layer 310. Insulating substrate 306 is typically sapphire or silicon dioxide (SiO.sub.2). Because transistor 300 is fabricated on insulating substrate 306, no parasitic P/N junctions exist in transistor 300. The lack of a parasitic P/N junction in SOI transistor 300 prevents SOI transistor 300 from operating in the same manner as ESD device 100 (FIGS. 1 and 2) to provide ESD protection.
SOI devices have lateral P/N junctions which are formed between adjacent regions (e.g., regions 301 and 302) of a thin silicon layer (e.g., silicon layer 310). For a given silicon surface area, these lateral P/N junctions are typically much smaller in area than conventional vertical P/N junctions, which conduct both laterally and vertically. As a result, a lateral P/N junction typically cannot carry the same amount of current as vertical P/N junction for the same silicon surface area. This inherent limitation of SOI technology has contributed to the problem of providing ESD protection for SOI devices.
Several alternatives have been attempted to provide adequate ESD protection for SOI devices. In one alternative, an insulating layer of SiO.sub.2 is formed along the upper surface of a bulk silicon substrate. SOI devices are then fabricated on the SiO.sub.2 layer. Openings are formed in the SiO.sub.2 layer, and conventional ESD protection devices are fabricated in the underlying bulk silicon. (See, e.g., Chan et al., "Comparison of ESD Protection Capability of SOI and BULK CMOS Output Buffers", 1994 IEEE International Reliability Physics Proceedings. pp. 292-298) This alternative disadvantageously requires the use of an underlying silicon substrate and introduces additional processing steps, thereby increasing fabrication costs.
FIG. 4 illustrates another conventional SOI ESD protection circuit 400. (See, e.g., J. P. Whitehead and N. N. Duncan, "Design and Evaluation of CMOS-SOS On-Chip Input Protection Circuits", Electrostatic Discharge Damage in Electronics--Seminar Proceedings (1986) P.4.2/1-10.). Protection circuit 400 includes input resistor 402, protection diodes 403 and 404, and spark gap circuit 409. P-channel field effect transistor 407 and n-channel field effect transistor 408 form the input buffer (i.e., an inverter) to circuit 411. Each of transistors 407 and 408 is an SOI device. Input resistor 402, located between input pad 401 and node 410 of circuit 400, typically has a resistance greater than 1000 ohms to ensure power consumption during an ESD event and reduce the voltage provided at node 410. As a result, voltage stress on the gate oxide of transistors 407 and 408 and on circuit 411 is reduced. (See, e.g., Cohen and Caswell, "An Improved Input Protection Circuit for C-MOS/SOS Arrays", IEEE Transactions on Electron Devices, Vol. ED. 25, No. 8, Aug. 1978, pp 926-933; and W. Palumbo and M. P. Dugan, "Design and Characterization of Input Protection Networks for CMOS/SOS Applications", 1986 Electrical Overstress/Electrostatic Discharge Symposium Proceedings, (1986) pp. 182-187).
Input resistor 402 is typically a polysilicon resistor formed between two layers of SiO.sub.2. Because SiO.sub.2 is a poor thermal conductor, the high current carried by polysilicon input resistor 402 causes overheating, which in turn damages the resistor. Thus, input resistor 402 is a common failure point in SOI ESD protection circuit 400.
Moreover, because input resistor 402 is connected in series with the gates of transistors 407 and 408, input resistor 402 introduces an RC time delay to input signals applied to input pad 401 during normal operation of circuit 411. Such an RC time delay is undesirable in high speed circuits.
Spark gap circuit 409 dissipates a portion of the transient energy of an ESD event by allowing ESD current to arc from input pad 401 to ground supply rail 406 through spark gap circuit 409. Spark gap circuit 409 typically includes a pair of metal electrodes which are separated by free space and are substantially surrounded by layers of silicon dioxide (SiO.sub.2). Because SiO.sub.2 is a poor thermal conductor, excess heat can build up around spark gap circuit 409 during an ESD event, thereby causing damage to spark gap circuit 409. Spark gap circuit 409 is not an ideal element because optimal gap spacing and geometries are difficult to determine. Moreover, arcing is at least partially destructive to spark gap circuit 409, thereby reducing the effectiveness of spark gap circuit 409 during subsequent ESD events. Despite the shortcomings of spark gap circuit 409, ESD protection for SOI devices has been historically so troublesome that considerable attention has been devoted to the design and inclusion of spark gap circuits (See, e.g., U.S. Pat. No. 4,794,437, "Arc Gap for Integrated Circuits" by Palumbo).
Protection diodes 403 and 404 are either gated or non-gated lateral diodes. FIG. 5 shows an illustrative non-gated lateral SOI diode 500, which includes a silicon layer 510 fabricated on insulating layer 501. Silicon layer 510 includes p type region 502, n type region 503 and center region 504. Center region 504 can be an n-region, a p-region or an undoped region.
FIG. 6 shows an illustrative gated diode 600, which includes a silicon layer 610 fabricated on insulating layer 601. Silicon layer 610 includes p type region 602, n-type region 603 and center region 604. Center region 604 is an n-region, a p-region or an undoped region. Gate oxide 605 and gate electrode 606 are fabricated over silicon layer 610 as illustrated. Gate electrode 606 is either connected to n type region 603 (as illustrated), connected to p type region 602, or is connected to another circuit node.
If gated lateral diode 600 is used for diodes 403 and 404 (FIG. 4) in protection circuit 400, gate electrode 606 capacitively loads input pad 401. The lateral P/N junction of diode 600 also places a small capacitive load on input pad 401. (The lateral P/N junction of non-gated lateral diode 500 similarly introduces a small capacitive load). Thus, input resistor 402, connected in series with this capacitive load, introduces an RC delay to signals applied to input pad 401, thereby degrading the performance of circuitry connected to ESD protection circuit 400.
In the implementation of protection circuit 400, a relatively large area is devoted to spark gap circuit 409 and input resistor 402 compared to the area devoted to protection diodes 403 and 404. Spark gap circuit 409 and input resistor 402 each typically consumes approximately twice as much area as diodes 403 and 404. To minimize the area of circuit 400 and to minimize the capacitive loading associated with protection diodes 403 and 404, the sizes of lateral diodes 403 and 404 are kept relatively small, generally less than 200 .mu.m in lateral width.
Certain prior art SOI ESD protection circuits have a number of zener diodes connected in series between the Vdd and Vss voltage supply rails. (See, e.g., Cohen and Caswell, "An Improved Input Protection Circuit for C-MOS/SOS Arrays", IEEE Transactions on Electron Devices, Vol. ED. 25, No. 8, Aug. 1978, pp 928). Five series zener diodes are connected such that the zener diodes conduct in reverse breakdown mode during the relevant ESD events. The five series zener diodes must be five times wider than a single protection diode to provide the same current carrying capacity with the same voltage drop. The zener diodes therefore consume considerable layout area and are consequently expensive to implement on an IC in a distributed fashion.
In bulk devices, output pins and input/output (I/O) pins are somewhat self-protecting because of parasitic P/N junctions present in the output buffers of bulk devices. The parasitic P/N junctions present in these output buffers operate to protect the output buffers in a manner similar to that described above in connection with FIGS. 1 and 2. The output pins and I/O pins of SOI devices are generally not self-protecting because the output buffers of SOI devices lack parasitic P/N junctions. Furthermore, SOI devices have potentially higher transistor drain-to-source breakdown voltages than bulk devices (because the deep channel breakdown path typically available in bulk devices is not present in SOI devices). In spite of this, no output buffer ESD protection schemes are taught for prior art SOI devices.
Therefore, a need arises for an SOI ESD protection circuit which (1) effectively protects SOI integrated circuits from high voltage related stress, (2) minimizes additional process complexities, (3) can withstand a series of ESD events with minimal degradation in the level of ESD protection, (4) minimizes input, output, and I/O pin path delay, (5) minimizes damaging effects of localized heating during an ESD event, (6) avoids excessive physical area requirements, (7) provides protection for ESD events which occur across the voltage supply rails, and (8) equals or exceeds the performance of bulk MOS ESD protection circuits (i.e., approximately 2000 volts in a conventional human body model test) without exposure to the design risk of unpredictable results often obtained by using bulk parasitic elements.